SUBTRACTION Subtraction of B from A can be done by adding -B to A. We can then use the adder which we have already developed. In order to take the negative of a number, it is necessary to decide on a representation for negative numbers. The representation most commonly adopted uses the two's complement convention. If we subtract 0101 (binary) = 5 (decimal) from 1110 (binary) = 14 (decimal), we should get 1001 (binary) = 9 (decimal). We can only get 1001 (binary) as the sum of 1110 (binary) and another number if we ignore carry. Then 11001 (binary) = 1110 (binary) + (-0101) (binary), or (-0101) (binary) = 11001 (binary) - 1110 (binary) = 1011 (binary) This is the binary for 11 (decimal), or 16 - 5. To calculate the negative of a binary number using the two's complement convention, we invert each bit in the number (giving the one's complement), and then add one. Thus, (-0101) (binary) = 1010 (binary) + 0001 (binary) = 1011 (binary). Implementation of negation in hardware is done in an analogous manner: first, each bit is inverted (using a 'not' gate), and then one is added (using a half adder). a3 a2 a1 a0 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! not ! ! not ! ! not ! ! not ! !_______! !_______! !_______! !_______! ! ! ! ! ! _____ ! _____ ! _____ ! ______ 1 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! half ! ! ! half ! ! ! half ! ! ! half ! ! adder ! ! ! adder ! ! ! adder ! ! ! adder ! !_______! ! !_______! ! !_______! ! !_______! ! ! ! ! ! ! ! ! ! ! ! C ____! ! !______! ! !______! ! !______! ! ! ! ! ! ! ! ! ! n3 n2 n1 n0 THE SR AND T FLIP-FLOPS Until now, we have concentrated on devices whose outputs are a function only of their current inputs. Such devices are called combinational logic circuits. It is possible to build another class of devices (sequential logic circuits), whose outputs depend not only on their current inputs, but also on their past inputs. Such devices are, then, capable of storing binary data. The simplest sequential logic curcuit is called the set-reset (or SR) flip-flop: ________ ________ ___! 1 ! _______! 2 ! S ---!___! nand !-----/ ___! nand !----+---- Q !________! ! !________! ! ! ________ ! ________ ___! 3 ! !___! 4 ! ! _ R ---!___! nand !----- _______! nand !----+---- Q !________! !________! ______ S ----!______!---- Q _ (Symbol for SR flip-flop.) R ----!______!------ Q Assume that, initially, S = R = 0, and Q = 0. Then the outputs of nand gates 1 and 3 are both 1. The inputs of nand gate 4 are then 0 and 1, and so its output (Q bar) is 1. Then the inputs of nand gate 2 are both 1, and so the output (Q) of nand gate 3 is 0 as originally stated. If S is now changed to 1, the output of nand gate 1 becomes 0, and so the inputs to nand gate 2 are now 1 and 0, and so its output (Q) becomes 1. This means that the inputs to nand gate 4 are now both 1, and so the output (Q bar) becomes 0. Finally, the inputs to nand gate 2 are both 0, and so its output is remains at the new value of 1. If S is now changed back to 0, the output of nand gate 1 becomes 1, and so the inputs to nand gate 2 are now 1 and 0. This means that its present output (Q) of 1 remains unchanged. Similarly, changing S back to 1 again does not alter the outputs: the flip-flop is set. To reset the flip-flop (change the value of Q to 0), it is necessary to change the value of R to 1 when S = 0. If R is changed to 1, the output of nand gate 3 becomes 0, and so the inputs to nand gate 4 are 0 and 1. Its output (Q bar) then becomes 1, and so the inputs to nand gate 2 are now both 1. The output of nand gate 2 (Q) then becomes 0. There are two major problems associated with the SR flip-flop. The first is that it is possible to have S and R both equal to 1. This would be an attempt to set and reset the flip-flop at the same time, and is logically meaningless. It is the responsibility of the logic designer to ensure that this situation is never allowed to occur. It is best, in fact, to ensure by means of external logic that, once the flip-flop is set, it is not possible to set it again until it is reset. Likewise, once it is reset, it should not be possible to reset it again until it is set. The second problem is that the inputs are not gated with a control or clock input. This means that it is not possible to synchronise the operation of two or more inputs to a single external clock. The second problem can be overcome by having a third, or clock input (T). The resulting flip-flop is called a clocked SR or T flip-flop: ________ ________ S _______! 1 ! _______! 2 ! ___! nand !-----/ ___! nand !----+---- Q ! !________! ! !________! ! ! ! T ___! ! ! ________ ! ________ !___! 3 ! !___! 4 ! ! _ R _______! nand !----- _______! nand !----+---- Q !________! !________! _________ S _____! !_____ Q T _____!_________! _ (Symbol for T flip-flop.) R _____! !_____ Q !_________! The clock input is used to connect the flip-flop to an external clock, and is used to synchronise its operation with other flip- flops. It has a waveform as follows: A ___ ___ ___ ___ Voltage ! ! ! ! ! ! ! ! ! ! ___! !___! !___! !___! !___ ! ----------------> time The T flip-flop behaves like the SR flip-flop, provided T = 1. If T = 0, then no change can occur to the outputs when S or R is changed. This means that it is possible to synchronise the operation of several flip-flops by simultaneously setting T to 1 on each of them. However, it still suffers from an indeterminate state when S and R are both equal to 1. THE JK MASTER SLAVE FLIP-FLOP The JK master slave flip-flop is more versatile than the SR or T flip-flops, and is probably the most widely used type. It contains two T flip-flops: __________________________________________ ! _______ _______ _______ ! !___! 1 ! ! ! ! ! ! J _____! and !-----! S Q'!-----! !--!--+----- Q !_______! !master ! ! slave ! ! ! T ________________.__!_______! __!_______! ! ! _______ ! ! ! ! ! ! ! ! K _____! 2 ! ! ! _ ! ! ! ! ! ! _ ___! and !--!--! R Q'!--!--! !--+--!----- Q ! !_______! ! !_______! ! !_______! ! ! ! _______ ! ! ! ! ! ! ! ! ! +--! not !--+ ! ! !_______! ! !_____________________________________________! The JK master slave flip-flop has two distinct operation modes: J /= K and J = K. In the J /= K mode, and when J = K = 0, it behaves much like the T or SR flip-flop. However, it also can perform a useful function when J = K = 1. J /= K If the output is Q = 1 and Q bar = 0, and the inputs are J = 0 and K = 1, then, before a clock pulse is applied (T = 0), the inputs to 'and' gate 1 are J = 0 and Q bar = 0, and so the S input to the master flip-flop is 0. The inputs to 'and' gate 2 are K = 1 and Q = 1, and so the R input to the master flip-flop is 1. When a clock pulse is applied (T = 1), the outputs of the master flip-flop will be as follows: Q' = 0 and Q' bar = 1. The data cannot at this stage appear on the output of the slave flip- flop, because the inverter ('not' gate) resets the clock input to the slave flip-flop to 0. When T is returned to logic 0, the clock input of the slave flip-flop becomes 1, and so Q becomes 0 and Q bar becomes 1. When J /= K, the JK master slave flip-flop thus behaves like a T flip-flop, the difference being that the data on the J and K inputs do not affect the outputs until the logic 1 -> logic 0 transition of the clock input. J = K = 0. When J = K = 0, the outputs from 'and' gates 1 and 2 (and therefore the inputs S and R of the master flip-flop) will both be 0. As the master flip-flop is a T flip-flop, its output will then be unaltered when a clock pulse is applied. The same applies for the slave flip-flop when T changes from 1 to 0. Then, the outputs Q and Q bar are unaltered. J = K = 1. If J = K = 1, and Q = 0 and Q bar = 1, then the inputs to 'and' gate 1 (J and Q bar) are both 1, and so its output (the input S of the master flip-flop) is 1. The inputs to 'and' gate 2 are J = 1 and Q = 0, and so its output (the input R of the master flip- flop) is 0. When T is changed to 1, the outputs of the master flip-flop are Q' = 1 and Q' bar = 0. When T is changed back to 0, the clock input to the slave flip-flop becomes 1 (because of the inverter (5)), and so Q becomes 1 and Q bar becomes 0. On the next clock cycle, the outputs of the flip-flop are again inverted. Thus, when J = K = 1, the outputs Q and Q bar become inverted at each clock cycle. SHIFT REGISTERS A shift register accepts data from an input source, and then shifts it along a chain of JK master slave flip-flops, moving one flip-flop each clock cycle. T ___________________________________________ ! ! ! ! ! ___ ! ___ ! ___ ! ___ A ---+---------!--! !--!--! !--!--! !--!--! !----- ! ___ +--!---! +--!---! +--!---! +--!---! +--!not!-----!___!-----!___!-----!___!-----!___!----- 1 2 3 4 A 4 bit shift register A is the value of the current input data, and T is the value of the current clock input. There are four JK master slave flip- flops, operating in J /= K mode. Each JK master slave flip- flop contains two T flip-flops: a master flip-flop and a slave flip-flop. When T is changed from 0 to 1, the value of A is transferred from the input of master flip-flop 1 to the input of slave flip- flop 1. Simultaneously, the value of the output of flip-flop X (where X = 1 to 3) is transferred from the input of master flip- flop X+1 to the input of slave flip-flop X+1. When T is changed from 1 to 0, the value of A appears on the output of slave flip- flop 1. The value of the output of flip-flop X (which is at present on the input of slave flip-flop X+1), appears on the output of slave flip-flop X+1. Thus, after each clock cycle, the data held on each flip-flop (except the last) are transferred to the following flip-flop, and the input data are transferred to the the first flip-flop. The data held on the last flip-flop are lost.