MAIN MEMORY ACCESS The SR flip-flop is the simplest flip-flop, and is adequate for storing data. Therefore it can be used as the basic storage unit in main-memory. Each memory cell has the following structure: select -----------------+-------------------------+ ! ! ! ------ +-------+ ! ------ +---! ! ! ! +--! ! output +---------!---! AND !--!S Q!--+ ! AND !--------- ! ! +-! 1 ! ! ! +----! 3 ! input ! ! ! ------ ! ! ------ -------+ ! ! ! ! ! ! ! ------ ! ! ! ------ +-!-! ! ! _! +-! NOT !---!-! AND !--!R Q! ------ +-! 2 ! ! ! write ! ------ +-------+ -------------------+ This can be writtem schematically as +------+ -----!S ! -----!I O!------ -----!W ! +------+ A three-input AND gate gives 1 as an output only if all of its inputs are 1. If any are 0, the output is zero. A three-input input AND gate can be constructed from two two-input and gates as follows: ------ input1 -------! ! ! AND !--+ ------ input2--------! ! +--! ! output ------ ! AND !----------- input3--------------------! ! ------ If select is 0, the memory cell is not selected. The output is 0, because the select input of AND gate 3 is 0. Also, the outputs of the SR flip-flop are unchanged, because both S and R are 0. This is caused by the outputs of AND gates 1 and 2 being 0, which is caused by the select inputs to AND gates 1 and 2 being 0. If select is 1, the cell can be written to if write is also 1. There are two cases: Input is 0. The output of AND gate 1 is 0, and the output of AND gate 2 is 1, and so the flip flop gets reset. The inputs of AND gate 3 are 1 (select) and 0 (Q), and so output becomes 0, the value of input. Input is 1. The output of AND gate 1 is 1, and the output of AND gate 2 is 0, and so the flip-flop gets reset. The inputs of AND gate 3 are 1 (select) and 1 (Q), and so output becomes 1, the value of input. A diagram of a four word memory (three bits per word) is shown, with associated registers MAR and MDR, and read/write control line. Data inputs: I1 I2 I3 (from MDR) ! ! ! ! ! ! +-----------!-+----------!-+----------!-+ ! ! ! +----+ ! ! +----+ ! ! +----+ ! ! +-!S ! ! +-! ! ! +-! ! MAR ! +---!I O!-+ +---! !-+ +---! !-+ ! ! ! +-!W ! ! ! +-! ! ! ! +-! ! ! V ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! +------+ ! +-!-+--------!-!-+--------!-!-+ ! +-+ ! ! ! ! ! ! ! ! ! ! !S!-! D 00 !-+ +-------!-!-+--------!-!-+--------!-!-+ ! !R! ! E ! ! ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! +-+ ! C 01 !---+ ! ! +-! ! ! ! +-! ! ! ! +-! ! ! ! O ! ! +---! !-+ +---! !-+ +---! !-+ +-+ ! D 10 !---+ ! ! +-! ! ! ! +-! ! ! ! +-! ! ! !S!-! E ! ! ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! !R! ! R 11 !-+ ! +-!-+--------!-!-+--------!-!-+ ! +-+ ! ! ! ! ! ! ! ! ! ! ! +------+ ! +-------!-!-+--------!-!-+--------!-!-+ ! ! ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! ! ! ! +-! ! ! ! +-! ! ! ! +-! ! ! ! ! +---! !-+ +---! !-+ +---! !-+ ! ! ! +-! ! ! ! +-! ! ! ! +-! ! ! ! ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! ! +-!-+--------!-!-+--------!-!-+ ! ! ! ! ! ! ! ! ! +---------!-!-+--------!-!-+--------!-!-+ ! ! ! ! +----+ ! ! ! +----+ ! ! ! +----+ ! ! ! +-! ! ! ! +-! ! ! ! +-! ! ! ! +---! !-+ +---! !-+ +---! !-+ ! +-! ! ! +-! ! ! +-! ! ! ! ! +----+ ! ! +----+ ! ! +----+ ! write ----------+---+--------!---+--------!---+ ! ! ! ! read ---------------------+-!----------+-!----------+ ! ! ! ! ! ! ! ----- ----- ----- ! AND ! ! AND ! ! AND ! ----- ----- ----- ! ! ! Data outputs: O1 O2 O3 (to MDR) The output lines from the memory cells must have the property that when at least one of them is 1, the output line becomes 1. This is called a wired OR. If MAR is 01, the 01 output from the decoder becomes 1, and the other decoder outputs become 0. The select line for the memory cells in the second row becomes 1, and so these cells can be read or modified (the select lines for all the other cells are all zero). If the read input is then set to 1, the values on the output lines O1, O2 and O3 become the values in the memory cells in the second row. Alternatively, if the write input is set to 1, memory cells in the second row take the values on the input lines I1, I2, I3. This type of memory is called a linear-select or 1-dimensional memory. For very large memories of this type, the decoder becomes very large. For this reason, 2- or higher dimensional memories are more frequently used. These use two decoders, each decoder taking half of MAR as its input. The memory cells in 2- dimensional memories require a second select input. This second input is connected to each of the AND gates in the memory cell. 2-dimensional memories use two very much simpler decoders than the equivalent 1-dimensional memory. READ ONLY MEMORY A read-only memory is not modified when an attempt to write to it is made. It can be constructed as an array of diodes. A diode is a type of valve (in modern computers it is made out of semiconductor materials). It allows current to pass through it easily in one direction, but gives a very high resistance to current in the opposite direction. +------+ ! ! ! ! ! D 00 !---!---!---!---!----- +-+ ! E ! ! ! ! ! !M!-->--! C 01 !---!---!---!---!----- !A! ! O ! ! ! ! ! !R!-->--! D 10 !---!---!---!---!----- +-+ ! E ! ! ! ! ! ! R 11 !---!---!---!---!----- +------+ ! ! ! ! O1 O2 O3 O4 A simple 4 word ROM If the input to the decoder from MAR is 01, the second row will be selected, and 0110 will appear on the outputs O1 to O4.