PRINCIPLES AND IMPLEMENTATION OF INSTRUCTION CODES ================================================== Processor Architecture Internal Structure of a simple 8-bit processor. To memory From / to memory A ! A ! ! ! ! V ! +---------------+ +---------------+ ! MAR (16 bits) ! R/W ! MDR (8 bits) ! +---------------+ +---------------+ ! ! A ! ! ! ! +---------------<---------------------+ ! ! ! [9] V [8] ! ! +----------------+ A ! +-[1]->-! ! ! ! ! ALU !----->------+ +----[2]->-! ! ! ! +----------------+ V ! ! ! +-------------+ ! +---<-[3a]---! A (8 bits) !---<-[3b]----+ ! +-------------+ ! ! ! ! +---------------+ ! +---<-[4a]--! PC (16 bits) !---<-[4b]---+ ! +---------------+ ! ! ! ! +---------------+ ! +---<-[5a]--! SP (16 bits) !---<-[5b]---+ ! +---------------+ ! ! ! ! +---------------+ ! +---<-[6a]--! T (16 bits) !---<-[6b]---+ +---------------+ ! ! +-------------+ ! ! IR (8 bits) !----<-[7]----+ +-------------+ ! V ! +-----------------+ ! CONTROL ! ! UNIT ! +-----------------+ CPU Registers and Data Paths. ----------------------------- The central processing unit (CPU) contains a number of registers, an arithmetic and logical unit (ALU), and a control unit, connected together by data paths or buses. The ALU contains the logic gates used to perform arithmetic and logical operations such as ADD, SUBTRACT, AND and OR. The control unit controls which data paths are used during execution of instructions. This particular processor is a one address machine: that is, most of the instructions take one main memory address as their single argument. Typical instructions are a := m[500] ;Put the contents of memory location 500 ;into the accumulator. a + m[4] ;Add the contents of memory location 4 to ;the contents of the accumulator, and store ;the sum in the accumulator. m[64] := a ;Store the contents of the accumulator in ;memory location 64. The particular notation used for the instructions is largely a matter of taste; if a different assembler is used, the above instructions could be written as load (500) add (4) store (64) The accumulator holds intermediate results in calculations. Its contents are determined by the memory locations accessed and the operations performed. The accumulator holds 8 data bits. This is the width of the data bus on this particular processor. PC and SP stand for program counter and stack pointer respectively, and are similar in function to registers R7 and R6 on the PDP-11. The program counter holds the address of the instruction being currently executed, and the stack pointer is used in subroutine calls and returns, and may be used to save the contents of the accumulator. Each of these registers bits wide, which is the width of the address bus. T is a temporary store, used in certain instructions. It is 16 bits wide. IR stands for instruction register. It contains the code of the instruction being executed, and is used by the control unit to determine which data paths are to be used during the instruction. Because the instructions are read as data, each instruction is 8 bits wide, with possibly an address of 16 bits following. Hence IR is an 8 bit register. MAR and MDR stand for memory address register and memory data register. MAR contains the address of the location from which data are read from or written to. If the instruction involves a data write, the contents of MDR are written to the memory location whose address is contained in MAR. If the instruction involves a data read, the contents of the memory location whose address is held in MAR are read into MDR. MAR is on the address bus and is 16 bits wide; MDR is on the data bus and is 8 bits wide. The numbers in square brackets on the data paths represent transmission gates. The transmission gates control data flow inside the processor, and are in turn controlled by the control unit. The processor operates by first fetching an instruction from memory and then executing it. During the fetch cycle, the following occurs: The contents of the program counter (PC) are placed in the memory address register (MAR). The program counter is then incremented by one. The read/write control line is then set to read. The next instruction is fetched from memory and put in the memory data register (MDR). It is then moved to the instruction register (IR). This could be written symbolically as mar := pc ; [4a] and [9] open pc + 1 ; [4a], [2] and [4b] open read ; R/W set to read ir := mdr ; [1] and [7b] open The transmission gates used are shown. The operation could be accomplished in two stages: firstly, [9], [2], [4a] and [4b] are opened and R/W is set to read. This causes the contents of PC to be moved into MAR (through [4a] and [9]), and, at the same time, into the ALU (through [4a] and [2]), where they are incremented, and then returned to the PC (through [4b]). When the data is fetched (accomplished by setting R/W to read), [7] is opened. This causes the data in MDR to be read into IR. The execute cycle follows the fetch cycle. What happens during the execute cycle depends on the instruction in IR which was fetched during the fetch cycle. For the instruction A + 10 (add 10 to the contents of the accumulator), the following occurs: The contents of the PC are placed in MAR, and then PC is incremented by one. The read/write control line is then set to read, causing the instructions parameter (in this case, 10) to be fetched from memory and put in MDR. The contents of MDR are then added to the contents of the accumulator and then stored in the accumulator. This could be written symbolically as mar := pc ; same as for fetch cycle pc + 1 ; read ; a + mdr ; [3a], [2], [1] and [3b] opened We have so far avoided the problem of how to move 16 bits of data (e.g. the PC's contents) along an 8-bit data bus. This is accomplished by treating each 16-bit register as two 8-bit registers. Supposing we have two 16-bit registers connected by a bus, thus: +----+ 1 +----+ 3 +----+ 4 +----+ ! XU !->-! XL !-------->----------! YU !->-! YL ! +----+ +----+ 8-bit data bus +----+ +----+ ! 2 ! ! 5 ! +---<---+ +---<---+ Moving the contents of X into Y is accomplished in two stages. First, the contents of YU are moved into YL, the contents of XL are moved into YU and XU, and the contents of XU are moved into XL. During this operation, transmission gates 1, 2, 3 and 4 are open. This is repeated, after which the entire contents of X are moved into Y. XU, XL -------------- YU, YL (contents before operation) XL, XU -------------- XL, YU (after first stage complete) XU, XL -------------- XU, XL (after second stage complete) The whole operation requires two clock cycles. Generally, 8-bit data moves within the processor require one clock cycle, and 16-bit bata moves require two clock cycles. This two-stage operation can be written symbolically as follows (assuming the existence of registers X and Y): yu := xl; yu := xl; Note that the registers are rotated during these instructions. The ALU has its own internal transmission gates, which are also controlled by the control unit. Stack Manipulation and Subroutine Instructions These instructions are more complex than simple arithmetic or logical instructions, such as addition, data store, and exclusive or. The execution cycles are shown, together with the transmission gates used (see page 1) push: ;Put the contents of the accumulator on the ;top of the stack. sp + 1 ;[5a], [2], [5b] open mar := sp ;[5a] and [9] open mdr := a ;[3a], [2], and [8] open write ;set R/W control line to write Note that gate [9] cannot be opened until SP has been incremented. pop: ;Put the contents of the top of the stack in ;the accumulator. mar := sp ; sp - 1 ; read ; a := mdr ; callx: ;Call the subroutine at memory location x. mar := pc ; read ; tu := mdr; ;Two memory data fetches, one for each byte pc + 1 ;of the address. TU is shifted into TL tu := mdr ;during these operations. pc + 1 ; sp + 1 ; mar := sp ; mdr := pcl ;Put the contents of PC in memory at the write ;address held in SP. sp + 1 ; mar := sp ; mdr := pcl ; write ; pc := temp ;Put the new address in the PC. return: mar := sp ;Read the return address from memory read ;(held on the top of the stack), and put pcu := mdr ;it in PC. sp - 1 ; mar := sp ; read ; pcu := mdr ; pcu := pcl ;Swap upper & lower bytes of PC. sp - 1 ; Note that these instructions are not the machine language instructions for the processor, but merely a convenient way of representing the flow of data inside the processor. Some of the operations can be executed concurrently, others (such as moving data from MDR to another register) have to wait for data to arrive before they can be performed, and there are also operations which cannot be performed concurrently because they would use the same data paths, which is forbidden. It is left as an exercise for the reader to determine which transmission gates are open during the last few instructions. A number of important details have not been covered in this lecture, such as how to read and write from memory and what transmission gates are. These (and other topics) will be covered in later lectures. A full instruction set for this processor will be designed. This will involve adding extra registers to the processor. It should also be noted that this is not the only processor architecture in use. It has some similarities with other one- address 8-bit machines, such as the Z80 and the Burroughs 90. There are zero address machines (such as the Burroughs 6800), and two address machines (such as the PDP-11). There are also dataflow machines, which do not have a program counter. These other architectures will also be examined in later lectures.